Low Warpage Coreless Substrate for IC Packages

Coreless substrate is excellent for fine patterning, small via pitches, and transmission property, and it is a promising IC packaging method for the next generation. Warpage of coreless substrate is generally large compared to the other types of IC packaging substrates because of inadequate rigidity, so the most important problem for the application of coreless substrates for high-end BGAs is warpage reduction during a reflow process. So far, only a limited number of reports have been focused on coreless substrates for large size IC packages. Moreover, very few examples have discussed substrate layer structural designs for warpage reduction and reliability improvement in IC assembly processes. In our study, we focused on the development of coreless substrates for large size ICs. To achieve our goal, we adopted the following development procedure. First, we designed analytical models with different layer structures composed of two kinds of insulating materials and estimated the effective layer structures for warpage reduction by numerical analysis. Next, we prepared the real coreless substrates with the same structure as the analytical models and evaluated their actual thermal behavior. Finally, we investigated the thermal stress reliability of IC mounted substrates. As results of these examinations, we successfully developed low warpage and high reliable coreless substrate by introducing high rigidity materials only in the external layers of the substrate.